CNDP  22.08.0
acl.h
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1 /* SPDX-License-Identifier: BSD-3-Clause
2  * Copyright (c) 2010-2022 Intel Corporation
3  */
4 
5 #ifndef _ACL_H_
6 #define _ACL_H_
7 
13 #ifdef __cplusplus
14 extern "C" {
15 #endif /* __cplusplus */
16 
17 #define CNE_ACL_QUAD_MAX 5
18 #define CNE_ACL_QUAD_SIZE 4
19 #define CNE_ACL_QUAD_SINGLE UINT64_C(0x7f7f7f7f00000000)
20 
21 #define CNE_ACL_SINGLE_TRIE_SIZE 2000
22 
23 #define CNE_ACL_DFA_MAX UINT8_MAX
24 #define CNE_ACL_DFA_SIZE (UINT8_MAX + 1)
25 
26 #define CNE_ACL_DFA_GR64_SIZE 64
27 #define CNE_ACL_DFA_GR64_NUM (CNE_ACL_DFA_SIZE / CNE_ACL_DFA_GR64_SIZE)
28 #define CNE_ACL_DFA_GR64_BIT (CHAR_BIT * sizeof(uint32_t) / CNE_ACL_DFA_GR64_NUM)
29 
30 typedef int bits_t;
31 
32 #define CNE_ACL_BIT_SET_SIZE ((UINT8_MAX + 1) / (sizeof(bits_t) * CHAR_BIT))
33 
34 struct cne_acl_bitset {
35  bits_t bits[CNE_ACL_BIT_SET_SIZE];
36 };
37 
38 #define CNE_ACL_NODE_DFA (0 << CNE_ACL_TYPE_SHIFT)
39 #define CNE_ACL_NODE_SINGLE (1U << CNE_ACL_TYPE_SHIFT)
40 #define CNE_ACL_NODE_QRANGE (3U << CNE_ACL_TYPE_SHIFT)
41 #define CNE_ACL_NODE_MATCH (4U << CNE_ACL_TYPE_SHIFT)
42 #define CNE_ACL_NODE_TYPE (7U << CNE_ACL_TYPE_SHIFT)
43 /*
44  * Each ACL RT contains an idle nomatch node:
45  * a SINGLE node at predefined position (CNE_ACL_DFA_SIZE)
46  * that points to itself.
47  */
48 #define CNE_ACL_IDLE_NODE (CNE_ACL_DFA_SIZE | CNE_ACL_NODE_SINGLE)
49 
50 #define CNE_ACL_NODE_UNDEFINED UINT32_MAX
51 
52 /*
53  * ACL RT structure is a set of multibit tries (with stride == 8)
54  * represented by an array of transitions. The next position is calculated
55  * based on the current position and the input byte.
56  * Each transition is 64 bit value with the following format:
57  * | node_type_specific : 32 | node_type : 3 | node_addr : 29 |
58  * For all node types except CNE_ACL_NODE_MATCH, node_addr is an index
59  * to the start of the node in the transitions array.
60  * Few different node types are used:
61  * CNE_ACL_NODE_MATCH:
62  * node_addr value is and index into an array that contains the return value
63  * and its priority for each category.
64  * Upper 32 bits of the transition value are not used for that node type.
65  * CNE_ACL_NODE_QRANGE:
66  * that node consist of up to 5 transitions.
67  * Upper 32 bits are interpreted as 4 signed character values which
68  * are ordered from smallest(INT8_MIN) to largest (INT8_MAX).
69  * These values define 5 ranges:
70  * INT8_MIN <= range[0] <= ((int8_t *)&transition)[4]
71  * ((int8_t *)&transition)[4] < range[1] <= ((int8_t *)&transition)[5]
72  * ((int8_t *)&transition)[5] < range[2] <= ((int8_t *)&transition)[6]
73  * ((int8_t *)&transition)[6] < range[3] <= ((int8_t *)&transition)[7]
74  * ((int8_t *)&transition)[7] < range[4] <= INT8_MAX
75  * So for input byte value within range[i] i-th transition within that node
76  * will be used.
77  * CNE_ACL_NODE_SINGLE:
78  * always transitions to the same node regardless of the input value.
79  * CNE_ACL_NODE_DFA:
80  * that node consists of up to 256 transitions.
81  * In attempt to conserve space all transitions are divided into 4 consecutive
82  * groups, by 64 transitions per group:
83  * group64[i] contains transitions[i * 64, .. i * 64 + 63].
84  * Upper 32 bits are interpreted as 4 unsigned character values one per group,
85  * which contain index to the start of the given group within the node.
86  * So to calculate transition index within the node for given input byte value:
87  * input_byte - ((uint8_t *)&transition)[4 + input_byte / 64].
88  */
89 
90 /*
91  * Structure of a node is a set of ptrs and each ptr has a bit map
92  * of values associated with this transition.
93  */
94 struct cne_acl_ptr_set {
95  struct cne_acl_bitset values; /* input values associated with ptr */
96  struct cne_acl_node *ptr; /* transition to next node */
97 };
98 
99 struct cne_acl_classifier_results {
100  int results[CNE_ACL_MAX_CATEGORIES];
101 };
102 
103 struct cne_acl_match_results {
104  uint32_t results[CNE_ACL_MAX_CATEGORIES];
105  int32_t priority[CNE_ACL_MAX_CATEGORIES];
106 };
107 
108 struct cne_acl_node {
109  uint64_t node_index; /* index for this node */
110  uint32_t level; /* level 0-n in the trie */
111  uint32_t ref_count; /* ref count for this node */
112  struct cne_acl_bitset values;
113  /* set of all values that map to another node
114  * (union of bits in each transition.
115  */
116  uint32_t num_ptrs; /* number of ptr_set in use */
117  uint32_t max_ptrs; /* number of allocated ptr_set */
118  uint32_t min_add; /* number of ptr_set per allocation */
119  struct cne_acl_ptr_set *ptrs; /* transitions array for this node */
120  int32_t match_flag;
121  int32_t match_index; /* index to match data */
122  uint32_t node_type;
123  int32_t fanout;
124  /* number of ranges (transitions w/ consecutive bits) */
125  int32_t id;
126  struct cne_acl_match_results *mrt; /* only valid when match_flag != 0 */
127  union {
128  char transitions[CNE_ACL_QUAD_SIZE];
129  /* boundaries for ranged node */
130  uint8_t dfa_gr64[CNE_ACL_DFA_GR64_NUM];
131  };
132  struct cne_acl_node *next;
133  /* free list link or pointer to duplicate node during merge */
134  struct cne_acl_node *prev;
135  /* points to node from which this node was duplicated */
136 };
137 
138 /*
139  * Types of tries used to generate runtime structure(s)
140  */
141 enum {
142  CNE_ACL_FULL_TRIE = 0,
143  CNE_ACL_NOSRC_TRIE = 1,
144  CNE_ACL_NODST_TRIE = 2,
145  CNE_ACL_NOPORTS_TRIE = 4,
146  CNE_ACL_NOVLAN_TRIE = 8,
147  CNE_ACL_UNUSED_TRIE = 0x80000000
148 };
149 
151 #define CNE_ACL_MAX_TRIES 8
152 
154 #define CNE_ACL_NAMESIZE 32
155 
156 struct cne_acl_trie {
157  uint32_t type;
158  uint32_t count;
159  uint32_t root_index;
160  const uint32_t *data_index;
161  uint32_t num_data_indexes;
162 };
163 
164 struct cne_acl_bld_trie {
165  struct cne_acl_node *trie;
166 };
167 
168 struct cne_acl_ctx {
169  char name[CNE_ACL_NAMESIZE];
171  enum cne_acl_classify_alg alg;
172  uint32_t first_load_sz;
173  void *rules;
174  uint32_t max_rules;
175  uint32_t rule_sz;
176  uint32_t num_rules;
177  uint32_t num_categories;
178  uint32_t num_tries;
179  uint32_t match_index;
180  uint64_t no_match;
181  uint64_t idle;
182  uint64_t *trans_table;
183  uint32_t *data_indexes;
184  struct cne_acl_trie trie[CNE_ACL_MAX_TRIES];
185  void *mem;
186  size_t mem_sz;
187  struct cne_acl_config config; /* copy of build config. */
188 };
189 
190 int cne_acl_gen(struct cne_acl_ctx *ctx, struct cne_acl_trie *trie,
191  struct cne_acl_bld_trie *node_bld_trie, uint32_t num_tries, uint32_t num_categories,
192  uint32_t data_index_sz, size_t max_size);
193 
194 typedef int (*cne_acl_classify_t)(const struct cne_acl_ctx *, const uint8_t **, uint32_t *,
195  uint32_t, uint32_t);
196 
197 /*
198  * Different implementations of ACL classify.
199  */
200 int cne_acl_classify_scalar(const struct cne_acl_ctx *ctx, const uint8_t **data, uint32_t *results,
201  uint32_t num, uint32_t categories);
202 
203 int cne_acl_classify_sse(const struct cne_acl_ctx *ctx, const uint8_t **data, uint32_t *results,
204  uint32_t num, uint32_t categories);
205 
206 int cne_acl_classify_avx2(const struct cne_acl_ctx *ctx, const uint8_t **data, uint32_t *results,
207  uint32_t num, uint32_t categories);
208 
209 int cne_acl_classify_avx512x16(const struct cne_acl_ctx *ctx, const uint8_t **data,
210  uint32_t *results, uint32_t num, uint32_t categories);
211 
212 int cne_acl_classify_avx512x32(const struct cne_acl_ctx *ctx, const uint8_t **data,
213  uint32_t *results, uint32_t num, uint32_t categories);
214 
215 int cne_acl_classify_neon(const struct cne_acl_ctx *ctx, const uint8_t **data, uint32_t *results,
216  uint32_t num, uint32_t categories);
217 
218 int cne_acl_classify_altivec(const struct cne_acl_ctx *ctx, const uint8_t **data, uint32_t *results,
219  uint32_t num, uint32_t categories);
220 
221 #ifdef __cplusplus
222 }
223 #endif /* __cplusplus */
224 
225 #endif /* _ACL_H_ */
#define CNE_ACL_MAX_TRIES
Definition: acl.h:151
#define CNE_ACL_NAMESIZE
Definition: acl.h:154
cne_acl_classify_alg
Definition: cne_acl.h:140
uint32_t num_categories
Definition: cne_acl.h:68
size_t max_size
Definition: cne_acl.h:72